High speed (large bandwidth) communication systems often require a memory to buffer the incoming data of multiple channels. Present FIFO (first in first out) memories for this application have a flag logic block for each channel. The flag logic blocks are configured to address a certain depth of memory based on the associated channel's data rate or bandwidth. Each of these logic blocks may potentially need to address the full memory space. As a result each logic block needs to compute and manage pointers and flags on all the address bits of memory. This results in the system having a significant amount of logic gates dedicated to computing and managing pointers and flags.
Thus there exists a need for a FIFO memory system for multiple input channels.